參數(shù)資料
型號(hào)： MCF5270AB100
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Integrated Microprocessor Hardware Specification
中文描述： 集成的微處理器，硬件規(guī)格
文件頁(yè)數(shù)： 9/40頁(yè)
文件大?。?/td> 863K
代理商： MCF5270AB100
Design Recommendations
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 2
Freescale Semiconductor
9
5.2.1
Supply Voltage Sequencing and Separation Cautions
Figure 1
shows situations in sequencing the I/O V
DD
(OV
DD
), PLL V
DD
(PLLV
DD
), and Core V
DD
(V
DD
).
OV
DD
is specified relative to V
DD
.
Figure 1. Supply Voltage Sequencing and Separation Cautions
5.2.1.1
Power Up Sequence
If OV
DD
are powered up with V
DD
at 0 V, then the sense circuits in the I/O pads will cause all pad output
drivers connected to the OV
DD
to be in a high impedance state. There is no limit on how long after OV
DD
powers up before V
DD
must powered up. V
DD
should not lead the OV
DD
or PLLV
DD
by more than 0.4 V
during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times
on the power supplies should be slower than 1
μ
s to avoid turning on the internal ESD protection clamp
diodes.
The recommended power up sequence is as follows:
1. Use 1
μ
s or slower rise time for all supplies.
2. V
DD
/PLLV
DD
and OV
DD
should track up to 0.9 V, then separate for the completion of ramps with
OV
DD
going to the higher external voltages. One way to accomplish this is to use a low drop-out
voltage regulator.
5.2.1.2
Power Down Sequence
If V
DD
/PLLV
DD
are powered down first, then sense circuits in the I/O pads will cause all output drivers to
be in a high impedance state. There is no limit on how long after V
DD
and PLLV
DD
power down before
OV
DD
must power down. V
DD
should not lag OV
DD
or PLLV
DD
going low by more than 0.4 V during
Supplies Stable
2
1
3.3V
2.5V
1.5V
0
Time
Notes:
1.
VDD should not exceed OVDD or PLLVDD by more than 0.4 V
at any time, including power-up.
Recommended that VDD/PLLVDD should track OVDD up to
0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD,
VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.
2.
3.
4.
D
V
DD
, PLLV
DD
OV
DD
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