MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8 Electrical Characteristics F" />
參數(shù)資料
型號(hào): MCF52277CVM160J
廠商: Freescale Semiconductor
文件頁數(shù): 24/46頁
文件大?。?/td> 0K
描述: IC MCU V2 32BIT 196MAPBGA
標(biāo)準(zhǔn)包裝: 126
系列: MCF5227x
核心處理器: Coldfire V2
芯體尺寸: 32-位
速度: 166.67MHz
連通性: CAN,EBI/EMI,I²C,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,LCD,PWM,WDT
輸入/輸出數(shù): 55
程序存儲(chǔ)器類型: ROMless
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.4 V ~ 1.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 196-LBGA
包裝: 托盤
MCF5227x ColdFire Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor
30
Figure 17. RESET and Configuration Override Timing
NOTE
Refer to the CCM chapter of the MCF52277 Reference Manual for more information.
5.10
LCD Controller Timing Specifications
This sections lists the timing specifications for the LCD Controller.
Figure 18. LCD_LSCLK to LCD_D[17:0] timing diagram
Table 19. LCD_LSCLK Timing
Num
Characteristic
Min
Max
Unit
T1
LCD_LSCLK Period
25
2000
ns
T2
Pixel data setup time
11
ns
T3
Pixel data up time
11
ns
Note: The pixel clock is equal to LCD_LSCLK / (PCD + 1). When it is in CSTN, TFT, or monochrome mode with
bus width = 1, LCD_LSCLK is equal to the pixel clock. When it is in monochrome with other bus width
settings, LCD_LSCLK is equal to the pixel clock divided by bus width. The polarity of LCD_LSCLK and
LCD_D signals can also be programmed.
R1
R2
FB_CLK
RESET
RSTOUT
R3
R4
R8
R7
R6
R5
Configuration Overrides*:
R4
(RCON, Override pins)
T1
T2
T3
LCD_LSCLK
LCD_D[17:0]
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