Index
I-6
MCF5206 USER’S MANUAL
MOTOROLA
INDEX
PRE-FINAL
DRAFT
bursting write,
6-18
burst-inhibited read,
6-21, 6-39
burst-inhibited write
6-42
longword-read
6-11
longword-write
8-9
operation,
6-6
word-write
6-14
debug interrupt
14-36
debug module
BDM connector
14-38
breakpoint
14-35
command set,
14-7
CPU32 functionality
14-4
processor status,
14-2
programming model,
14-27
real-time debug
14-27
serial interface,
14-6
signals,
2-16
Default Memory
8-40
default memory
8-37
Default Memory Control Register (DMCR)
8-37
double bus fault
6-5
DRAM
access permissions,
10-7
alternate master use
10-40, 10-50, 10-60
burst page mode
10-47
burst page mode,
10-32, 10-54
bus arbitration,
10-30
fast page mode
10-50, 10-54, 10-56, 10-57
fast page mode operation,
10-20
initialization
10-61
limitations
10-50
normal mode
10-54
normal mode operation
10-15
normal mode,
10-41, 10-44
page hit,
10-23, 10-25
page miss,
10-27
programming model
10-51
refresh operation,
10-38
signals,
2-13
DRAM Controller Address Registers (DCAR0-1)
10-
58
DRAM Controller Control Register (DCCR0-1)
10-
60
DRAM Controller Mask Register (DCMR0-1)
10-59
DRAM Controller Refresh Register (DCRR)
10-51
DRAM Controller Timing Register (DCTR)
10-52
E
EDO DRAM
10-35, 10-53, 10-56, 10-57
exceptions
access errors,
1-5
bus,
6-5
external bus master
6-53
F
fast page mode
10-20, 10-27, 10-50, 10-54, 10-
56, 10-57
FIFO stack
11-11
fill buffer
4-1
H
halt
14-5
I
implicit ownership state
6-60
index sizing, index scaling, program counter indi-
rect, register indirect
1-8
Instructions
STOP
1-5
TRAP
1-5
internal reset
6-81, 6-84
interrupt acknowledge cycles
6-47, 6-48, 11-16
Interrupt Control Register (ICR)
7-9
interrupt exception
6-47
Interrupt Mask Register (IMR)
7-11
interrupt masking
6-47
interrupt signals
2-7
Interrupt-Pending Register (IPR)
7-12
interrupts
1-5
external,
7-4, 7-6
handling
11-33
M-BUS
7-5
requests (UART)
11-3
software watchdog
7-5
software watchdog,
7-3
spurious,
7-2
timer
7-5
UART,
7-5
J
JTAG
boundary-scan register,
15-6
BYPASS instruction,
15-5
CLAMP instruction
15-5
HIGHZ instruction,
15-4
IDCODE instruction,
15-4
IDcode register,
15-5
SAMPLE/PRELOAD instruction
15-4
signals,
2-18
L
logical address space
1-8
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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