Figure 13. Deviation of DCO Output Across " />
參數(shù)資料
型號(hào): MCF51QE96CLK
廠商: Freescale Semiconductor
文件頁數(shù): 14/38頁
文件大小: 0K
描述: IC MCU 32BIT 96K FLASH 80-LQFP
產(chǎn)品培訓(xùn)模塊: Flexis QE Series Low Power Features
標(biāo)準(zhǔn)包裝: 90
系列: MCF51QE
核心處理器: Coldfire V1
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,SCI,SPI
外圍設(shè)備: LVD,PWM,WDT
輸入/輸出數(shù): 70
程序存儲(chǔ)器容量: 96KB(96K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 24x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-LQFP
包裝: 托盤
Electrical Characteristics
MCF51QE128 Series Data Sheet, Rev. 7
Freescale Semiconductor
21
Figure 13. Deviation of DCO Output Across VDD at 25°C
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
3.10.1
Control Timing
Table 13. Control Timing
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
1D
Bus frequency (tcyc = 1/fBus)
VDD ≥ 1.8V
VDD > 2.1V
VDD > 2.4V
fBus
dc
10
20
25.165
MHz
2
D
Internal low power oscillator period
tLPO
700
1300
μs
3
D
External reset pulse width2
textrst
100
ns
4
D
Reset low drive
trstdrv
34 x tcyc
——
ns
5D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
ns
6D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
μs
-0.50%
-0.40%
-0.30%
-0.20%
-0.10%
0.00%
0.10%
0.20%
0.30%
0.40%
0.50%
2.1V
2.4V
2.7V
3.0V
3.3V
3.6V
VDD
%
deviation
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