參數(shù)資料
型號(hào): MCF51CN128CLK
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 14 MM, 1.40 MM HEIGHT, 0.65 MM PITCH, LQFP-80
文件頁(yè)數(shù): 20/48頁(yè)
文件大小: 3550K
代理商: MCF51CN128CLK
Electrical Characteristics
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
Freescale Semiconductor
27
Figure 19. Reset Timing
Figure 20. IRQ/KBIPx Timing
6D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
μs
7D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
2 x tcyc
ns
8D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
2 x tcyc
ns
9C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
16
23
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
5
9
ns
10
C
Stop3 recovery time, from interrupt event to vector fetch
tSTPREC
—6
10
μs
1 Typical values are based on characterization data at V
DD = 3.3 V, 25 °C unless otherwise stated.
2 This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not
guaranteed to override reset requests from internal sources.
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
4 This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt
request until it is explicitly negated by the interrupt service routine.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 °C to 85 °C.
Table 17. Control Timing (continued)
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
textrst
RESET PIN
tIHIL
KBIPx
tILIH
IRQ/KBIPx
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