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參數(shù)資料
| 型號(hào)： | MCCF68HC08LK60 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC150 |
| 封裝： | 0.226 X 0.242 INCH, BUMP, WAFER-150 |
| 文件頁數(shù)： | 21/248頁 |
| 文件大小： | 1727K |
| 代理商： | MCCF68HC08LK60 |
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IRQ Module During Break Interrupts
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
Freescale Semiconductor
117
Vector fetch, software clear, or reset — A vector fetch generates an interrupt acknowledge signal
to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to
the ACK2 bit in the interrupt status and control register (ISCR). The ACK2 bit is useful in
applications that poll the IRQ2 pin and require software to clear the IRQ2 interrupt latch. Writing to
the ACK2 bit can also prevent spurious interrupts due to noise. Setting ACK2 does not affect
subsequent transitions on the IRQ2 pin. A falling edge that occurs after writing to the ACK2 bit
latches another interrupt request. If the IRQ2 mask bit, IMASK2, is clear, the CPU loads the
program counter with the vector address at locations $FFD2 and $FFD3.
Return of the IRQ2 pin to logic 1 — As long as the IRQ2 pin is at logic 0, the IRQ2 interrupt latch
remains set.
The vector fetch or software clear and the return of the IRQ2 pin to logic 1 may occur in any order. The
interrupt request remains pending as long as the IRQ2 pin is at logic 0.
If the MODE2 bit is clear, the IRQ2 pin is falling-edge-sensitive only. With MODE2 clear, a vector fetch or
software clear immediately clears the IRQ2 interrupt latch.
To determine the logic level on the IRQ2 pin, read the IRQ2 pin state bit, PIN2, in the ISCR. This bit
reflects the value of the IRQ2 pin, even when the IRQ2DIS bit is set.
NOTE
See Chapter 19 Keyboard Interrupt (KBI) Module for more information
about keyboard interrupt.
11.4 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ1 and IRQ2 interrupt latches can be
cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear the latches during the break state. (See 6.7.3 SIM Break Flag Control Register.)
To allow software to clear the IRQ1 latch and the IRQ2 interrupt latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits
the break state.
To protect the latches during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its
default state), writing to the ACK1 and ACK2 bits in the IRQ status and control register during the break
state has no effect on the IRQ latches. See 11.5 IRQ Status and Control Register.
11.5 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. It has
these functions:
Shows current state of IRQ2 pin
Clears the IRQ1 and IRQ2 interrupt latches
Masks IRQ1 and IRQ2 interrupt requests
Controls triggering sensitivity of the IRQ1 and IRQ2 interrupt pins
Disables IRQ2 interrupt requests
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