參數(shù)資料
型號(hào)： MCCF68HC08LK60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC150
封裝： 0.226 X 0.242 INCH, BUMP, WAFER-150
文件頁(yè)數(shù)： 185/248頁(yè)
文件大?。?/td> 1727K
代理商： MCCF68HC08LK60
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FLASH1 Block Protect Register
MC68HC08LK60 MC68HC908LK60 Advance Information Data Sheet, Rev. 1.1
Freescale Semiconductor
41
PGM — Program control bit
This read/write bit configures the memory for program operation. It is interlocked with the ERASE bit
such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
4.6 FLASH1 Block Protect Register
The block protect register is implemented as an input/output (I/O) register. Each bit, when programmed,
protects a range of addresses in the FLASH.
BPR3 — Block protect register bit 3
This bit protects the memory contents in the address range $C000–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR2 — Block protect register bit 2
This bit protects the memory contents in the address range $A000–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR1 — Block protect register bit 1
This bit protects the memory contents in the address range $9000–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR0 — Block protect register bit 0
This bit protects the memory contents in the address range $8000–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
By programming the block protect bits, a portion of the memory will be locked so that no further erase or
program operations may be performed. Programming more than one bit at a time is redundant. For
instance, if both BPR3 and BPR2 are set, the address range $A000–$FFFF is locked. If all bits are
cleared, then all of the memory is available for erase and program.
Address:
$0033
Bit 7
654321
Bit 0
Read:
Write:
BPR3
BPR2
BPR1
BPR0
Reset:
XXXX
1111
= Unimplemented
X = Indeterminate
Figure 4-4. FLASH1 Block Protect Register (FL1BPR)
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