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參數(shù)資料
| 型號： | MC9SDJ64MPVR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP112 |
| 封裝： | LQFP-112 |
| 文件頁數(shù)： | 56/102頁 |
| 文件大?。?/td> | 1007K |
| 代理商： | MC9SDJ64MPVR2 |
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MC9S12DJ64 Device User Guide — V01.02
57
Consult the PIM_9DJ64 Block User Guide for information about the Port Integration Module.
Section 20 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins(C1 - C6).
Central point of the ground star should be the VSSR pin.
Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
VSSPLL must be directly connected to VSSR.
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
Central power input should be fed in at the VDDA/VSSA pins.
Component
Purpose
Type
Value
C1
VDD1 lter cap
ceramic X7R
100 .. 220nF
C2
VDD2 lter cap
ceramic X7R
100 .. 220nF
C3
VDDA lter cap
ceramic X7R
100nF
C4
VDDR lter cap
X7R/tantalum
>=100nF
C5
VDDPLL lter cap
ceramic X7R
100nF
C6
VDDX lter cap
X7R/tantalum
>=100nF
C7
OSC load cap
C8
OSC load cap
C9
PLL loop lter cap
See PLL specication chapter
C10
PLL loop lter cap
C11
DC cutoff cap
R1
PLL loop lter res
Q1
Quartz
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