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參數(shù)資料
| 型號(hào)： | MC9S12UF32PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 60 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁數(shù)： | 105/128頁 |
| 文件大?。?/td> | 1785K |
| 代理商： | MC9S12UF32PB |
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System on a Chip Guide — 9S12UF32DGV1/D V01.05
78
Freescale Semiconductor
Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12UF32. Each mode has an
associated default memory map and external bus configuration. In addition each operating mode, with the
exception of Special Peripheral Mode (SPM), can be configured for low power operation by entering one
of two low power sub-modes. The device is also equipped with security features which restrict certain
modes of operation and limit access to internal memory. More detailed information on the various
operating modes, and their configurations can be found in the HCS12 V1.5 Core User Guide.
4.2 Modes of Operation
There are two basic categories of operating modes:
1.
Normal modes: Some registers and bits are protected against accidental changes.
2.
Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
In all Normal and Special modes a system development and debug feature, background debug mode
(BDM), is available. In special single-chip mode, BDM is active immediately after reset.
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal. When resetting into all modes except
SPM, the ESTR bit in the EBICTL register is set to one, configuring the ECLK as a bus control signal, to
assure that the reset vector can be fetched even if it located in an external slow memory device.
The following sections discuss the default bus setup and describe which aspects of the bus can be changed
after reset on a per mode basis.
Table 4-1 Mode Selection
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
Mode Description
00
0
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all
other modes but a serial command is required to make BDM active.
0
1
Emulation Expanded Narrow, BDM allowed
0
1
0
Special Test (Expanded Wide), BDM allowed
0
1
Emulation Expanded Wide, BDM allowed
1
0
Normal Single Chip, BDM allowed
1
0
1
Normal Expanded Narrow, BDM allowed
11
0
Special Peripheral; BDM allowed but bus operations would cause bus
conicts (must not be used)
1
Normal Expanded Wide, BDM allowed
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