參數(shù)資料
型號(hào)： MC9S12P96J0CQK
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP80
封裝： 14 X 14 MM, 0.65 MM PITCH, QFP-80
文件頁(yè)數(shù)： 52/528頁(yè)
文件大小： 6002K
代理商： MC9S12P96J0CQK
S12S Debug (S12SDBG) Module
S12P-Family Reference Manual, Rev. 1.07
Freescale Semiconductor
PRELIMINARY
145
6.4.4
State Sequence Control
Figure 6-24. State Sequencer Diagram
The state sequencer allows a dened sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then
state1 of the state sequencer is entered. Further transitions between the states are then controlled by the
state control registers and channel matches. From Final State the only permitted transition is back to the
disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the
SSF[2:0] ags in DBGSR accordingly to indicate the current state.
Alternatively writing to the TRIG bit in DBGSC1, provides an immediate trigger independent of
comparator matches.
Independent of the state sequencer, each comparator channel can be individually congured to generate an
immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers.
Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer
transition can be initiated by a match on other channels. If a debug session is ended by a match on a channel
the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing
and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and
the debug module is disarmed.
6.4.4.1
Final State
On entering Final State a trigger may be issued to the trace buffer according to the trace alignment control
as dened by the TALIGN bit (see 6.3.2.3”). If the TSOURCE bit in DBGTCR is clear then the trace buffer
Table 6-35. Channel Priorities
Priority
Source
Action
Highest
TRIG
Enter Final State
Channel pointing to Final State
Transition to next state as dened by state control registers
Match0 (force or tag hit)
Transition to next state as dened by state control registers
Match1 (force or tag hit)
Transition to next state as dened by state control registers
Lowest
Match2 (force or tag hit)
Transition to next state as dened by state control registers
State1
Final State
State3
ARM = 1
Session Complete
(Disarm)
State2
State 0
(Disarmed)
ARM = 0
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