
Analog-to-Digital Converter (ADC12B10C)
S12P-Family Reference Manual, Rev. 1.07
284
PRELIMINARY
Freescale Semiconductor
9.3.2.5
ATD Control Register 4 (ATDCTL4)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Table 9-11. ATD Behavior in Freeze Mode (Breakpoint)
FRZ1
FRZ0
Behavior in Freeze Mode
0
Continue conversion
0
1
Reserved
1
0
Finish current conversion, then freeze
1
Freeze Immediately
Module Base + 0x0004
76543210
R
SMP2
SMP1
SMP0
PRS[4:0]
W
Reset
00000101
Figure 9-7. ATD Control Register 4 (ATDCTL4)
Table 9-12. ATDCTL4 Field Descriptions
Field
Description
7–5
SMP[2:0]
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
Table 9-13 lists the available sample time lengths.
4–0
PRS[4:0]
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
is calculated as follows:
Refer to Device Specication for allowed frequency range of fATDCLK.
Table 9-13. Sample Time Select
SMP2
SMP1
SMP0
Sample Time
in Number of
ATD Clock Cycles
000
4
001
6
010
8
011
10
100
12
101
16
110
20
f
ATDCLK
f
BUS
2PRS
1
+
()
×
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