Table 22 and
參數(shù)資料
型號(hào): MC9S08MM64VLH
廠商: Freescale Semiconductor
文件頁數(shù): 33/52頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 32K FLASH 64LQFP
標(biāo)準(zhǔn)包裝: 160
系列: S08
核心處理器: S08
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SCI,SPI,USB
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 12K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x16b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 托盤
Electrical Characteristics
Freescale Semiconductor
39
2.12
SPI Characteristics
Table 22 and Figure 12 through Figure 15 describe the timing requirements for the SPI system.
Table 22. SPI Timing
No.1
1 Numbers in this column identify elements in Figure 12 through Figure 15.
Characteristic2
2 All timing is shown with respect to 20% V
DD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing
assumes slew rate control disabled and high drive strength enabled for SPI output pins.
Symbol
Min
Max
Unit
C
1
Operating frequency
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
D
2
SPSCK period
Master
Slave
tSPSCK
2
4
2048
tcyc
D
3
Enable lead time
Master
Slave
tLead
1
2
1
tSPSCK
tcyc
D
4
Enable lag time
Master
Slave
tLag
1
2
1
tSPSCK
tcyc
D
5
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc –30
tcyc – 30
1024 tcyc
ns
D
6
Data setup time (inputs)
Master
Slave
tSU
15
ns
D
7
Data hold time (inputs)
Master
Slave
tHI
0
25
ns
D
8
Slave access time3
3 Time to data active from high-impedance state.
ta
—1
tcyc
D
9
Slave MISO disable time4
4 Hold time to high-impedance state.
tdis
—1
tcyc
D
10
Data valid (after SPSCK edge)
Master
Slave
tv
25
ns
D
11
Data hold time (outputs)
Master
Slave
tHO
0
ns
D
12
Rise time
Input
Output
tRI
tRO
tcyc – 25
25
ns
D
13
Fall time
Input
Output
tFI
tFO
tcyc – 25
25
ns
D
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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