Table 18. MCG (Temperat" />
參數(shù)資料
型號(hào)： MC9S08MM64VLH
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 27/52頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8BIT 32K FLASH 64LQFP
標(biāo)準(zhǔn)包裝： 160
系列： S08
核心處理器： S08
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SCI，SPI，USB
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 33
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 12K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x16b，D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 64-LQFP
包裝： 托盤(pán)
Electrical Characteristics
Freescale Semiconductor
33
2.10
MCG and External Oscillator (XOSC) Characteristics
Table 18. MCG (Temperature Range = –40 to 105°C Ambient)
#
Rating
Symbol
Min
Typical
Max
Unit
C
1
Internal reference startup time
tirefst
—55
100
s
D
2
Average internal reference frequency
factory trimmed at
VDD=3.0 V and
temp=25
C
fint_ft
—
31.25
—
kHz
C
user trimmed
31.25
—
39.0625
C
3
DCO output frequency range —
trimmed
Low range
(DRS=00)
fdco_t
16
—
20
MHz
C
Mid range
(DRS=01)
32
—
40
C
High range1
(DRS=10)
1 This should not exceed the maximum CPU frequency for this device which is 48 MHz.
40
—
60
C
4
Resolution of trimmed DCO output fre-
quency at fixed voltage and tempera-
ture
with FTRIM
f
dco_res_t
—
0.1
0.2
%fdco
C
without FTRIM
—
0.2
0.4
C
5
Total deviation of trimmed DCO output
frequency over voltage and tempera-
ture
over voltage and
temperature
f
dco_t
—
1.0
2
%fdco
P
over fixed voltage
and temp range
of 0 – 70
C
—
0.5
1
C
6
Acquisition time
FLL2
2 This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
tfll_acquire
——
1
ms
C
PLL3
tpll_acquire
——
1
D
7
Long term Jitter of DCO output clock (averaged over 2mS
interval) 4
CJitter
—0.02
0.2
%fdco
C
8
VCO operating frequency
fvco
7.0
—
55.0
MHz
D
9
PLL reference frequency range
fpll_ref
1.0
—
2.0
MHz
D
10
Jitter of PLL output clock measured
over 625ns 5
Long term
fpll_jitter_625
ns
—
0.5664
—
%fpll
D
11 Lock frequency tolerance
Entry6
Dlock
1.49
—
2.98
%
D
Exit7
Dunl
4.47
—
5.97
D
12 Lock time
FLL
tfll_lock
——
tfll_acquire+
1075(1/fint_t)
s
D
PLL
tpll_lock
——
tpll_acquire+
1075(1/fpll_re
f)
D
13
Loss of external clock minimum frequency - RANGE = 0
floc_low
(3/5) x
fint_t
—
kHz
D
14
Loss of external clock minimum frequency - RANGE = 1
floc_high
(16/5) x
fint_t
—
kHz
D
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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