Introduction
MC9S08GB/GT Data Sheet, Rev. 2.3
Freescale Semiconductor
99
7.1
Introduction
Figure 7-3 is a top-level diagram that shows the functional organization of the internal clock generation
(ICG) module. This section includes a general description and a feature list.
Figure 7-3. ICG Block Diagram
The ICG provides multiple options for clock sources. This offers a user great exibility when making
choices between cost, precision, current draw, and performance. As seen in Figure 7-3, the ICG consists
of four functional blocks. Each of these is briey described here and then in more detail in a later section.
Oscillator block — The oscillator block provides means for connecting an external crystal or
resonator. Two frequency ranges are software selectable to allow optimal startup and stability.
Alternatively, the oscillator block can be used to route an external square wave to the system clock.
External sources can provide a very precise clock source.
Internal reference generator — The internal reference generator consists of two controlled clock
sources. One is designed to be approximately 8 MHz and can be selected as a local clock for the
background debug controller. The other internal reference clock source is typically 243 kHz and
can be trimmed for ner accuracy via software when a precise timed event is input to the MCU.
This provides a highly reliable, low-cost clock source.
OSCILLATOR (OSC)
FREQUENCY
INTERNAL
EXTAL
XTAL
REFERENCE
GENERATORS
CLOCK
SELECT
8 MHz
IRG
LOSS OF LOCK
AND CLOCK DETECTOR
LOCKED
LOOP (FLL)
FIXED
CLOCK
SELECT
ICGOUT
TYP 243 kHz
RG
ICGLCLK
ICG
FFE
VDDA
V SSA
(SEE NOTE 2)
DCO
WITH EXTERNAL REF
SELECT
REF
SELECT
LOCAL CLOCK FOR OPTIONAL USE WITH BDC
OUTPUT
CLOCK
SELECT
ICGDCLK
/R
ICGERCLK
ICGIRCLK
NOTES:
1. See
Figure 7-1 for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK
2. Not all HCS08 microcontrollers have unique supply pins for the ICG. See the device pin assignments in
the Pins and Connections section for specifics.