參數(shù)資料
型號: MC9328MXSVF10
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, MICROPROCESSOR, PBGA225
封裝: 13 X 13 MM, PLASTIC, BGA-225
文件頁數(shù): 17/72頁
文件大小: 1411K
代理商: MC9328MXSVF10
MC9328MXS Advance Information, Rev. 0
24
Freescale Semiconductor
Specifications
3.9.2.6 WAIT Read Cycle DMA Enabled
Figure 11. WAIT Read Cycle DMA Enabled
Table 18. WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1OE and EB assertion time
See note 2
ns
2CS pulse width
3T
ns
3OE negated before CS5 is negated
1.5T-0.68
1.5T-0.06
ns
4
Address inactived before CS negated
0.05
ns
5
Wait asserted after CS5 asserted
1020T
ns
6Wait asserted to OE negated
2T+1.57
3T+7.33
ns
7
Data hold timing after OE negated
T-1.49
ns
8
Data ready after wait is asserted
T
ns
9CS deactive to next CS active
T
ns
10
OE negate after EB negate
0.06
0.18
ns
11
Wait becomes low after CS5 asserted
0
1019T
ns
12
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
RW
WAIT
Address
EB
CS5
OE
(logic high)
DATABUS
programmable
min 0ns
1
2
3
8
9
5
6
7
11
10
12
4
(input to i.MX)
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