參數(shù)資料
型號: MC9328MXSCVP10R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, MICROPROCESSOR, PBGA225
封裝: 13 X 13 MM, ROHS COMPLIANT, PLASTIC, MAPBGA-225
文件頁數(shù): 46/68頁
文件大?。?/td> 1335K
代理商: MC9328MXSCVP10R2
Functional Description and Application Information
MC9328MXS Technical Data, Rev. 2
50
Freescale Semiconductor
4.7
Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in
Figure 42 and the parameters are listed in Table 21.
Figure 42. PWM Output Timing Diagram
T8
SCLK to valid LD data
-3
3
ns
T9
End of HSYN idle2 to VSYN edge
(for non-display region)
22
Ts
T9
End of HSYN idle2 to VSYN edge
(for Display region)
11
Ts
T10
VSYN to OE active (Sharp = 0) when VWAIT2 = 0
1
Ts
T10
VSYN to OE active (Sharp = 1) when VWAIT2 = 0
2
Ts
Note:
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 41, all 3 signals
are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period.
In Figure 41, SCLK is always active.
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
Table 20. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Symbol
Description
Minimum
Corresponding Register Value
Unit
System Clock
2a
1
PWM Output
3b
2b
3a
4b
4a
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