參數(shù)資料
型號: MC9328MXSCVF10
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, MICROPROCESSOR, PBGA225
封裝: 13 X 13 MM, PLASTIC, BGA-225
文件頁數(shù): 19/72頁
文件大小: 1411K
代理商: MC9328MXSCVF10
MC9328MXS Advance Information, Rev. 0
26
Freescale Semiconductor
Specifications
3.9.2.8 WAIT Write Cycle DMA Enabled
Figure 13. WAIT Write Cycle DMA Enabled
Table 20. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
CS5 assertion time
See note 2
ns
2EB assertion time
See note 2
ns
3CS5 pulse width
3T
ns
4RW negated before CS5 is negated
2.5T-3.63
2.5T-1.16
ns
5
Address inactived after CS negated
0.09
ns
6
Wait asserted after CS5 asserted
1020T
ns
7
Wait asserted to RW negated
T+2.66
2T+7.96
ns
8
Data hold timing after RW negated
2T+0.03
ns
9
Data ready after CS5 is asserted
T
ns
10
CS deactive to next CS active
T
ns
11
EB negate after CS negate
0.5T
0.5T+0.5
12
Wait becomes low after CS5 asserted
0
1019T
ns
13
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
OE
WAIT
Address
EB
CS5
RW
(logic high)
DATABUS
programmable
min 0ns
programmable
min 0ns
8
5
7
11
12
4
(output to i.MX)
1
2
3
10
6
13
9
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