參數(shù)資料
型號: MC9328MXLDVM15
廠商: Freescale Semiconductor
文件頁數(shù): 13/90頁
文件大?。?/td> 0K
描述: IC MCU I.MX 150MHZ 256-MAPBGA
標準包裝: 152
系列: i.MXL
核心處理器: ARM9
芯體尺寸: 32-位
速度: 150MHz
連通性: EBI/EMI,I²C,MMC/SD,SPI,SSI,UART/USART,USB
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 97
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: -30°C ~ 70°C
封裝/外殼: 256-LFBGA
包裝: 托盤
Functional Description and Application Information
MC9328MXL Technical Data, Rev. 8
20
Freescale Semiconductor
4
Functional Description and Application Information
This section provides the electrical information including and timing diagrams for the individual modules
of the i.MXL.
4.1
Embedded Trace Macrocell
All registers in the ETM9 are programmed through a JTAG interface. The interface is an extension of the
ARM920T processor’s TAP controller, and is assigned scan chain 6. The scan chain consists of a 40-bit
shift register comprised of the following:
32-bit data field
7-bit address field
A read/write bit
The data to be written is scanned into the 32-bit data field, the address of the register into the 7-bit address
field, and a 1 into the read/write bit.
A register is read by scanning its address into the address field and a 0 into the read/write bit. The 32-bit
data field is ignored. A read or a write takes place when the TAP controller enters the UPDATE-DR state.
The timing diagram for the ETM9 is shown in Figure 2. See Table 9 for the ETM9 timing parameters used
Figure 2. Trace Port Timing Diagram
Table 9. Trace Port Timing Diagram Parameter Table
Ref No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
1
CLK frequency
0
85
0
100
MHz
2a
Clock high time
1.3
2
ns
2b
Clock low time
3
2
ns
3a
Clock rise time
4
3
ns
3b
Clock fall time
3
3
ns
TRACECLK
4b
4a
3b
2a
1
Output Trace Port
3a
Valid Data
2b
TRACECLK
(Half-Rate Clocking Mode)
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