參數(shù)資料
型號: MC9328MXLDVM15
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 150 MHz, RISC PROCESSOR, PBGA256
封裝: 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, MAPBGA-256
文件頁數(shù): 57/89頁
文件大小: 1869K
代理商: MC9328MXLDVM15
60
MC9328MXL Advance Information
MOTOROLA
Specifications
Active which sets up the status register read. The bank and row addresses are driven during this command.
The third command of the triplet is Read. Bank and column addresses are driven on the address bus during
this command. Data is returned from memory on the low order 8 data bits following the CAS latency.
Figure 48. SDRAM/SyncFlash Read Cycle Timing Diagram
Table 22. SDRAM Timing Parameter Table
Ref
No.
Parameter
1.8V ± 0.10V
3.0V ± 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
1
SDRAM clock high-level width
2.67
4
ns
2
SDRAM clock low-level width
6—4—
ns
3
SDRAM clock cycle time
11.4
10
ns
3S
CS, RAS, CAS, WE, DQM setup time
3.42
3
ns
SDCLK
CS
CAS
WE
RAS
ADDR
DQ
DQM
ROW/BA
COL/BA
3S
3H
3S
3H
3S
3S
3H
4S
4H
5
3S
3
2
1
8
Data
7
6
Note:
CKE is high during the read/write cycle.
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