參數(shù)資料
型號： MC9328MXLCVM15R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
封裝： 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256
文件頁數(shù)： 75/90頁
文件大?。?/td> 1242K
代理商： MC9328MXLCVM15R2
Functional Description and Application Information
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
77
Figure 62. SSI Receiver External Clock Timing Diagram
Table 33. SSI (Port C Primary Function) Timing Parameter Table
Ref No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
Internal Clock Operation1 (Port C Primary Function2)
1
STCK/SRCK clock period1
95
–
83.3
–
ns
2
STCK high to STFS (bl) high3
1.54.5
1.33.9
ns
3
SRCK high to SRFS (bl) high3
-1.2
-1.7
-1.1
-1.5
ns
4
STCK high to STFS (bl) low3
2.54.3
2.23.8
ns
5
SRCK high to SRFS (bl) low3
0.1
-0.8
0.1
-0.8
ns
6
STCK high to STFS (wl) high3
1.48
4.45
1.3
3.9
ns
7
SRCK high to SRFS (wl) high3
-1.1
-1.5
-1.1
-1.5
ns
8
STCK high to STFS (wl) low3
2.51
4.33
2.2
3.8
ns
9
SRCK high to SRFS (wl) low3
0.1
-0.8
0.1
-0.8
ns
10
STCK high to STXD valid from high impedance
14.25
15.73
12.5
13.8
ns
11a
STCK high to STXD high
0.91
3.08
0.8
2.7
ns
11b
STCK high to STXD low
0.57
3.19
0.5
2.8
ns
12
STCK high to STXD high impedance
12.88
13.57
11.3
11.9
ns
13
SRXD setup time before SRCK low
21.1
–
18.5
–
ns
14
SRXD hold time after SRCK low
0
–
0
–
ns
External Clock Operation (Port C Primary Function2)
15
STCK/SRCK clock period1
92.8
–
81.4
–
ns
16
STCK/SRCK clock high period
27.1
–
40.7
–
ns
17
STCK/SRCK clock low period
61.1
–
40.7
–
ns
SRCK Input
16
SRFS (bl) Input
SRFS (wl) Input
17
19
23
SRXD Input
29
30
21
25
15
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MXL
Product
Family
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