參數(shù)資料
型號(hào)： MC9328MXLCVM15R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256
封裝： 14 X 14 MM, 1.30 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-256
文件頁(yè)數(shù)： 21/90頁(yè)
文件大?。?/td> 1242K
代理商： MC9328MXLCVM15R2
Functional Description and Application Information
MC9328MXL Technical Data, Rev. 8
28
Freescale Semiconductor
4.4.2.3
WAIT Write Cycle without DMA
Figure 8. WAIT Write Cycle without DMA
12
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1CS5 assertion time
See note 2
–
ns
2EB assertion time
See note 2
–
ns
3CS5 pulse width
3T
–
ns
4RW negated before CS5 is negated
2.5T-3.63
2.5T-1.16
ns
5RW negated to Address inactive
64.22
–
ns
6
Wait asserted after CS5 asserted
–
1020T
ns
Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
OE
WAIT
Address
EB
CS5
RW
(logic high)
DATABUS
programmable
min 0ns
programmable
min 0ns
1
2
3
8
5
6
7
11
10
12
4
from i.MXL
9
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MXL
Product
Family
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