參數(shù)資料
型號: MC9328MX21VK
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA289
封裝: 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-289
文件頁數(shù): 16/100頁
文件大小: 1979K
代理商: MC9328MX21VK
MC9328MX21 Technical Data, Rev. 3.4
22
Freescale Semiconductor
Specifications
Figure 6. MMD (ATI) Drives Clock, MMD Read BMI Timing
(MMD_MODE_SEL=1, MASTER_MODE_SEL=0,MMD_CLKOUT=0)
Note:
All the timings assume that the hclk is running at 133 MHz.
Note:
The MIN period of the 1T is assumed that MMD latch data at falling edge.
Note:
If the MMD latch data at next rising edge, the ideally max clock can be as much as double, but because the BMI data pads
are slow pads and it max frequency can only up to 18MHz, the max clock frequency can only up to 36 MHz.
3.8.1.1.2
MMD Write BMI Timing
Figure 7 shows the MMD write BMI timing when MMD drives clock. On each falling edge of BMI_CLK/
CS BMI checks the BMI_WRITE logic level to determine if the current cycle is a write cycle. If the BMI_
WRITE is logic low, it latches data into the RxFIFO on each falling edge of BMI_CLK/CS signal.
Table 14. MMD Read BMI Timing Table when MMD Drives Clock
Item
Symbol
Minimum
Typical
Maximum
Unit
Clock period
1T
33.3
ns
write setup time
Ts
11
ns
read_req hold time
Trh
6
24
ns
transfer data setup time
Tds
6
14
ns
transfer data hold time
Tdh
6
-
14
ns
BMI_CLK/CS
BMI_READ_REQ
BMI_WRITE
BMI_D[15:0]
TxD1
TxD2
Last TxD
Trh
1T
Tds
Ts
Tdh
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC9328MX21VK 制造商:Freescale Semiconductor 功能描述:Microprocessor
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