參數(shù)資料
型號(hào)： MC9328MX21VH
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 266 MHz, MICROPROCESSOR, PBGA289
封裝： 17 X 17 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, MAPBGA-289
文件頁(yè)數(shù)： 63/106頁(yè)
文件大?。?/td> 1932K
代理商： MC9328MX21VH
MC9328MX21 Product Preview, Rev. 1.1
6
Freescale Semiconductor
Signal Descriptions
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8], shared with SDRAM
DQM2 and PCMCIA PC_REG.
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0], shared with SDRAM
DQM3 and PCMCIA PC_IORD.
OE
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA
PC_IOWR.
CS [5:0]
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by
the Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD
[1:0] is selected. DTACK is multiplexed with CS4.
ECB
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an
on-going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
BCLK
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is
also shared with the PCMCIA PC_WE.
DTACK
DTACK signal—External input data acknowledge signal, multiplexed with CS4.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode of the i.MX21 upon system reset is
determined by the settings of these pins.
SDRAM Controller
SDBA [4:0]
SDRAM non-interleave mode bank address signals. These signals are multiplexed with address
signals A[20:16].
SDIBA [3:0]
SDRAM interleave addressing mode bank address signals. These signals are multiplexed with
address signals A[24:21].
MA [11:0]
SDRAM address signals. MA[9:0] are multiplexed with address signals A[10:1].
DQM [3:0]
SDRAM data qualifier mask multiplexed with EB[3:0]. DQM3 corresponds to D[31:24], DQM2
corresponds to D[23:16], DQM1 corresponds to D[15:8], and DQM0 corresponds to D[7:0].
CSD0
SDRAM Chip Select signal. This signal is multiplexed with the CS2 signal. This signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
CSD1
SDRAM Chip Select signal. This signal is multiplexed with the CS3 signal. This signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
RAS
SDRAM Row Address Select signal
CAS
SDRAM Column Address Select signal
SDWE
SDRAM Write Enable signal
SDCKE0
SDRAM Clock Enable 0
SDCKE1
SDRAM Clock Enable 1
SDCLK
SDRAM Clock
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
相關(guān)PDF資料
PDF描述
MC9328MX21CVG 266 MHz, MICROPROCESSOR, PBGA289
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC9328MX21VK 功能描述:處理器 - 專(zhuān)門(mén)應(yīng)用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類(lèi)型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX21VK 制造商:Freescale Semiconductor 功能描述:Microprocessor
MC9328MX21VKR2 功能描述:處理器 - 專(zhuān)門(mén)應(yīng)用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類(lèi)型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX21VM 功能描述:處理器 - 專(zhuān)門(mén)應(yīng)用 DB I.MX21 17X17 PB-FR RoHS:否 制造商:Freescale Semiconductor 類(lèi)型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX21VM 制造商:Freescale Semiconductor 功能描述:Microprocessor
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