參數(shù)資料
型號: MC9328MX21VH
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 266 MHz, MICROPROCESSOR, PBGA289
封裝: 17 X 17 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, MAPBGA-289
文件頁數(shù): 59/106頁
文件大?。?/td> 1932K
代理商: MC9328MX21VH
MC9328MX21 Product Preview, Rev. 1.1
56
Freescale Semiconductor
Specifications
27b
(Tx) CK high to STXD low
10.80
19.36
7.71
9.20
ns
28
(Tx) CK high to STXD high impedance
12.08
19.36
7.71
9.20
ns
29
SRXD setup time before (Rx) CK low
0.37
0.42
ns
30
SRXD hole time after (Rx) CK low
0
0
ns
Synchronous Internal Clock Operation (SAP Ports)
31
SRXD setup before (Tx) CK falling
23.00
21.41
ns
32
SRXD hold after (Tx) CK falling
0
0
ns
Synchronous External Clock Operation (SAP Ports)
33
SRXD setup before (Tx) CK falling
1.20
0.88
ns
34
SRXD hold after (Tx) CK falling
0
0
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
Table 33. SSI to SSI1 Ports Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
Internal Clock Operation1 (SSI1 Ports)
1
(Tx/Rx) CK clock period1
90.91
90.91
ns
2
(Tx) CK high to FS (bl) high
-0.68
-0.15
-0.68
-0.15
ns
3
(Rx) CK high to FS (bl) high
-0.96
-0.27
-0.96
-0.27
ns
4
(Tx) CK high to FS (bl) low
-0.68
-0.15
-0.68
-0.15
ns
5
(Rx) CK high to FS (bl) low
-0.96
-0.27
-0.96
-0.27
ns
6
(Tx) CK high to FS (wl) high
-0.68
-0.15
-0.68
-0.15
ns
7
(Rx) CK high to FS (wl) high
-0.96
-0.27
-0.96
-0.27
ns
8
(Tx) CK high to FS (wl) low
-0.68
-0.15
-0.68
-0.15
ns
9
(Rx) CK high to FS (wl) low
-0.96
-0.27
-0.96
-0.27
ns
Table 32. SSI to SAP Ports Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
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