參數(shù)資料
型號: MC9328MX21CVG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 266 MHz, MICROPROCESSOR, PBGA289
封裝: 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, MAPBGA-289
文件頁數(shù): 24/106頁
文件大小: 1932K
代理商: MC9328MX21CVG
MC9328MX21 Product Preview, Rev. 1.1
24
Freescale Semiconductor
Specifications
Figure 7. MMD (ATI) Drives Clock, MMD Write BMI Timing
(MMD_MODE_SEL=1, MASTER_MODE_SEL=0, MMD_CLKOUT=0)
Note: All timings assume that the hclk is running at 133 MHz.
Note: At this mode, the maximum frequency of the BMI_CLK/CS can be up to 36 MHz (doubles as maximum data pad speed).
3.8.1.2
BMI Drives the BMI_CLK/CS
In this mode MMD_MODE_SEL and MMD_CLKOUT are both set. The software must know which
mode it is now (READ or WRITE). When the BMI_WRITE is high, BMI drives BMI_CLK/CS out if the
TxFIFO is not emptied. When BMI_WRITE is low, user can write a 1 to READ bit of control register1 to
issue a write cycle (MMD write BMI).
3.8.1.3
MMD Read BMI Timing
Figure 13 on page 29 shows the MMD read BMI timing when BMI drives the BMI_CLK/CS. When the
BMI_WRITE is high, the BMI drives BMI_CLK/CS out if data is written to TxFIFO (BMI_READ_REQ
become high), BMI puts data into data bus and enable data out on the rising edge of BMI_CLK/CS. The
MMD devices can latch the data on each falling edge of BMI_CLK/CS.
It is recommended that the MMD do not change the BMI_WRITE signal from high to low when the
BMI_READ_REQ is asserted. If user writes data to the TxFIFO when the BMI_WRITE is low, the BMI
will drive BMI_CLK/CS out once the BMI_WRITE is changed from low to high.
Table 13. MMD Write BMI Timing
Item
Symbol
Minimum
Typical
Maximum
Unit
write setup time
Ts
11
ns
write hold time
Th
0
ns
receive data setup time
Tds
5
ns
Can be asserted any time
BMI_CLK/CS
BMI_READ_REQ
BMI_WRITE
BMI_D[15:0]
RxD1
RxD2
Last RxD
Ts
Tds
Th
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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