參數(shù)資料
型號(hào)： MC9328MX21CJMR2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 48/100頁(yè)
文件大小： 0K
描述： IC MCU 1.MX21 289-PBGA
標(biāo)準(zhǔn)包裝： 1,000
系列： i.MX21
核心處理器： ARM9
芯體尺寸： 32-位
速度： 266MHz
連通性： 1 線，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 192
程序存儲(chǔ)器類型： ROMless
電壓 - 電源 (Vcc/Vdd)： 1.45 V ~ 3.3 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 289-LFBGA
包裝： 帶卷 (TR)
Specifications
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
51
3.16
Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,
the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous
mode, the transmitter and receiver each have their own clock and frame synchronization signals.
Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated
clock mode, the clock functions only during transmission. The internal and external clock timing diagrams
are shown in Figure 42 through Figure 45.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
The SSI can be connected to 4 set of ports, SAP, SSI1, SSI2 and SSI3.
Figure 42. SSI Transmitter Internal Clock Timing Diagram
CK Output
FS (bl) Output
FS (wl) Output
1
2
6
8
10
11
STXD Output
SRXD Input
32
31
4
12
Note:
SRXD input in synchronous mode only.
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