參數(shù)資料
型號： MC9328MX1DVM15
廠商： Freescale Semiconductor
文件頁數(shù)： 57/100頁
文件大?。?/td> 0K
描述： IC MCU I.MX 150MHZ 256-MAPBGA
標準包裝： 152
系列： i.MX1
核心處理器： ARM9
芯體尺寸： 32-位
速度： 150MHz
連通性： EBI/EMI，I²C，MMC，智能卡，SPI，SSI，UART/USART，USB
外圍設備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 110
程序存儲器類型： ROMless
電壓 - 電源 (Vcc/Vdd)： 1.7 V ~ 3.3 V
振蕩器型： 外部
工作溫度： -30°C ~ 70°C
封裝/外殼： 256-MAPBGA
包裝： 托盤
Signals and Connections
MC9328MX1 Technical Data, Rev. 7
6
Freescale Semiconductor
DMA
DMA_REQ
DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY.
BIG_ENDIAN
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven
logic-low at reset, the external chip-select space will be configured to little endian. This input must not
change state after power-on reset negates or during chip operation.
ETM
ETMTRACESYNC
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETMTRACECLK
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETMPIPESTAT [2:0]
ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16].
ETMTRACEPKT [7:0] are selected in ETM mode.
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
CSI_VSYNC
Sensor port vertical sync
CSI_HSYNC
Sensor port horizontal sync
CSI_PIXCLK
Sensor port data latch clock
LCD Controller
LD [15:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
FLM/VSYNC
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
LP/HSYNC
Line pulse or H sync
LSCLK
Shift clock
ACD/OE
Alternate crystal direction/output enable.
CONTRAST
This signal is used to control the LCD bias voltage as contrast control.
SPL_SPR
Program horizontal scan direction (Sharp panel dedicated signal).
PS
Control signal output for source driver (Sharp panel dedicated signal).
CLS
Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated
signal).
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SIM
SIM_CLK
SIM Clock
SIM_RST
SIM Reset
SIM_RX
Receive Data
Table 2. i.MX1 Signal Descriptions (Continued)
Signal Name
Function/Notes
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相關代理商/技術參數(shù)
參數(shù)描述
MC9328MX1DVM15R2 功能描述:處理器 - 專門應用 DRAGONBALL MX1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX1DVM20 功能描述:處理器 - 專門應用 DRAGONBALL MX1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX1DVM20R2 功能描述:處理器 - 專門應用 DRAGONBALL MX1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MC9328MX1P/D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX Integrated Portable System Processor
MC9328MX1S 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:i.MX Integrated Portable System Processor
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