參數(shù)資料
型號: MC92600JUB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
封裝: 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217
文件頁數(shù): 38/98頁
文件大?。?/td> 1018K
代理商: MC92600JUB
MOTOROLA
Chapter 4. System Design Considerations
4-1
Chapter 4
System Design Considerations
This chapter describes the system considerations of the MC92600 Quad DDR, including
device-startup, initialization, and the proper use of the standby and repeater modes.
4.1
Reference Clock Conguration
The legal ranges of reference clock frequencies vary depending on the operating modes
selected. Table 4-1 shows the ranges allowed for each mode of operation.
4.2
Start-up
The MC92600 begins a start-up sequence upon application of the reference clock
(REF_CLK input) to the device. This is considered a cold start-up. The receiver requires
that byte alignment is reached before data can be transmitted. If word synchronization is
selected, then word alignment must occur. The steps in the cold start-up sequence are as
follows:
1. PLL start-up
2. Receiver initialization and byte alignment
3. Word alignment (if enabled)
4. Run
Table 4-1. Legal Reference Clock Frequency Ranges
DDRE
HSE
Reference Frequency
Min (MHz)
Reference Frequency
Max (MHz)
Link Transfer Rate
(Gigabaud)
Low
95.00
135.0
1.350–0.950
Low
High
47.50
67.50
0.675–0.475
High
Low
47.50
67.50
1.350–0.950
High
23.75
33.75
0.675–0.475
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