參數(shù)資料
型號： MC92600JUB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA217
封裝： 23 X 23 MM, 2.32 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-217
文件頁數(shù)： 16/98頁
文件大小： 1018K
代理商： MC92600JUB
MOTOROLA
Chapter 2. Transmitter
2-3
Transmitter Interface Signals
Table 2-1. MC92600 Transmitter Interface Signals
Signal Name
Description
Function
Direction
Active
State
XMIT_x_7 through
XMIT_x_0
Transmit byte
Uncoded data/control byte to transmit.
The least signicant 8 bits of coded data
to transmit in TBI mode.
Input
—
XMIT_x_K
Special data indicator
Indicates that transmit byte is a special
control byte. Must be decoded with
XMIT_x_IDLE and WSE_GEN to
determine action, see Table 2-2.
Coded transmit data bit 8 in TBI mode.
This signal also affects receiver
operation. See Section 3.2.
Input
High
XMIT_x_IDLE
Transmit idle character
bar
Transmit an idle character. Must be
decoded with XMIT_x_K and
WSE_GEN to determine action, see
Coded transmit data bit 9 in TBI mode.
Input
Low
WSE_GEN
Word synchronization
event generate
Transmit a disparity-style word
synchronization event. Must be
decoded with XMIT_x_IDLE and
XMIT_x_K to determine action, see
This signal also affects receiver
operation. See Section 3.2.
Input
High
LBE
Loop back enable
Activate digital loopback path, such that
data transmitted is looped back to its
receiver.
Input
High
LBOE
Loop back output
enable
Indicates that link outputs remains
active when LBE is asserted. When
LBOE is low, link outputs are disabled
when LBE is asserted.
Input
High
TBIE
10-bit interface enable
Indicates that coded 10-bit data is at
inputs and to bypass internal 8B/10B
coding.
Input
High
REPE
Repeater mode enable
When enabled, the transmitter obtains
transmit data from the receiver.
Input
High
HSE
Half speed enable
When enabled, link is operated at
half-speed. Both data and link
interfaces run at half speed.
Input
High
DDRE
Double data rate enable
Indicates that the data interfaces are
running at double data rate (data is
sampled on the rising and falling edges
of reference clock).
Input
High
REF_CLK
Reference clock
System reference clock to which the
transmit interfaces are timed.
Frequency requirement is dependent on
HSE and DDRE settings. See Section
3.6 and Table 3.6 for conguration
options.
Input
—
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相關代理商/技術參數(shù)
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