參數(shù)資料
型號(hào)： MC92600
廠商： Motorola, Inc.
英文描述： High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口)
中文描述： 高速，全雙工，串行數(shù)據(jù)接口（高速全雙工串行數(shù)據(jù)接口）
文件頁(yè)數(shù)： 31/82頁(yè)
文件大小： 1056K
代理商： MC92600
Chapter 3. WarpLink Receiver
3-9
Clock Modes
recovered clock is not generated by a clock recovery PLL, but is generated by the receiver
bit-accumulation and byte-alignment logic. The RECV_n_RCLK signal is asserted high,
generating a rising edge, whenever a new byte (character) is accumulated and available.
To track a transmitter frequency that is offset from the receivers reference clock frequency,
the duty cycle and period of the recovered clock is modulated. The WarpLink Quad is
designed to tolerate up to +250 ppm of frequency offset. For example: if the transmitter is
running 100 ppm faster than the receiver, then a short cycle is generated approximately
every 2,000 received bytes. The short cycle has a period equal to eight bit-times instead of
the normal ten bit-times. This implies that logic using received data timed to the recovered
clock must be able to operate with a period equal to eight bit-times (6.4 ns for 1.25
gigabaud). Short cycles recover two bits-times of offset. Generally, the number of received
bytes (characters) between short cycles is equal to:
(2 * 10
6
) / (10 * N) bytes
where:
N is the frequency offset in ppm.
Alternately, if the transmitter is running 100 ppm slower than the receiver, then a long cycle
is generated approximately every 2,000 received bytes. The long cycle has a period equal
to twelve bit-times instead of ten bit-times. The above equation is also used to compute the
period between long cycles.
Data is timed to the rising edge of the recovered clock signal except in double data rate
mode where data is timed to the rising and falling edges of the recovered clock.
If the receivers are being operated in word synchronization mode (WSE = high), the data
for all four receivers are timed relative to link As recovered clock RECV_A_RCLK.
NOTE:
Recovered clocks RECV_B_RCLK, RECV_C_RCLK, and
RECV_D_RCLK are not aligned to the data in word
synchronization mode and should not be used.
3.4.2 Reference Clock Mode
Data is timed relative to the reference clock when RCCE is low. Synchronization between
the recovered clock and the reference clock is handled by the receiver interface. Frequency
offset between the transmitters reference clock and the receivers reference clock causes
overrun/underrun situations. Overrun occurs when the transmitter is running faster than the
receiver. Underrun occurs when the transmitter is running slower than the receiver.
In an overrun situation, a byte of data needs to be dropped to maintain synchronization
between the clock domains. The receiver interface searches for an idle byte to drop when
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