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| 型號(hào)： | MC92460ZU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 40 CHANNEL(S), 66.7M bps, SERIAL COMM CONTROLLER, PBGA480 |
| 封裝： | 37 X 37 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, TBGA-480 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 353K |
| 代理商： | MC92460ZU |
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MC92460 Product Summary Page
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Semiconductors
MC92460 : Multichannel HDLC Controller Peripheral
The MC92460 is a 40-channel, high-level data link controller (HDLC) with an aggregate throughput of up
to 2 Gbps across a synchronous optical network (SONET). A total of eight of these peripheral devices can
be connected to the 60x bus of the MPC8260 or the MPC603e.
Applications for the MPC92460 include remote access concentrators, frame relay switches, high-speed
direct links, regional office routers, DSLAM (xDSL) and internet access equipment, and uses in the cellular
infrastructure.e.
MC92460 Features
Major features of the MC92460 include the following:
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Controllers
r
Maximum throughput of up to 2 Gbps; individual controllers operating up to 66.7 Mbps
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All communication controllers operating in asynchronous mode
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HDLC Channels
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40 dedicated full-duplex HDLC channels
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Each HDLC channel supporting a maximum of 66.7 Mbps
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A default of 64 buffer descriptors per channel (32 TxBD + 32 RxBD) or 4096 total buffer
descriptors
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Configurable number of buffer descriptors in each channel (minimum of 0, maximum of
4096)
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Buffering
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32-Kbyte on-chip dual port RAM for buffer descriptors
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A default of 64 buffer descriptors per channel (32 TxBD + 32 RxBD) or 4096 total buffer
descriptors
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256 Kbits on-chip memory for data buffers
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256-Kbit communication buffer storing up to 819 bytes per frame
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Maximum buffer length of 64 Kbytes
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80 channel virtual DMA functionality executing between off-chip memory and the
communications buffer
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Framing
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Programmable frame size (maximum 64 Kbytes)
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Flexible buffers and multiple buffers per frame
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Separate interrupts for frames and buffers (Tx and Rx)
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Received frames threshold to reduce interrupt overhead
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Flag/abort/idle generation and detection
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Zero insertion and deletion
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16- or 32-bit CRC-CCITT generation and checking
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Detection of non-connected aligned frames
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Detection of too-long frames
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Programmable flags (0-15) between successive frames
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Automatic retransmission in case of collision
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Echo and local loopback mode for testing
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Master interface unit
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Directly connects with 64-bit data, 32-bit address 60x bus
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