
Chapter 18 Memory Mapping Control (S12XMMCV3)
MC9S12XDP512 Data Sheet, Rev. 2.17
678
Freescale Semiconductor
Table 18-21 shows the address boundaries of each chip select and the relationship with the implemented
resources (internal) parameters.
Figure 18-23. Local to Implemented Global Address Mapping (Without GPAGE)
18.4.2.4
XGATE Memory Map Scheme
18.4.2.4.1
Expansion of the XGATE Local Address Map
The XGATE 64 Kbyte memory space allows access to internal resources only (Registers, RAM, and
FLASH). The 2 Kilobyte register address range is the same register address range as for the CPU and the
XGATE can access the FLASH in single chip modes, even when the MCU is secured. In expanded modes,
XGATE can not access the FLASH when MCU is secured.
The local address of the XGATE RAM access is translated to the global RAM address range. The XGATE
shares the RAM resource with the CPU and the BDM module (see
Table 18-22).XGATE RAM size (XGRAMSIZE) may be lower or equal to the MCU RAM size (RAMSIZE).
The local address of the XGATE FLASH access is translated to the global address as dened by
Example 18-3. is a general example of the XGATE memory map implementation.
Table 18-21. Global Chip Selects Memory Space
Chip Selects
Bottom Address
Top Address
CS3
0x00_0800
0x0F_FFFF minus RAMSIZE1
1 External RPAGE accesses in (NX, EX and ST)
CS2
0x10_0000
0x13_FFFF minus EEPROMSIZE2
2 External EPAGE accesses in (NX, EX and ST)
CS23
3 When ROMHM is set (see ROMHM in Table 18-19) the CS2 is asserted in the space occupied by this on-chip memory block.
0x14_0000
0x1F_FFFF
CS1
0x20_0000
0x3F_FFFF
CS04
the CS0 is not asserted in the space occupied by this on-chip memory block.
0x40_0000
0x7F_FFFF minus FLASHSIZE5
5 External PPAGE accesses in (NX, EX and ST)
Table 18-22. XGATE Implemented Memory Space
Internal Resource
$Address
XGATE RAM
XGRAM_LOW = 0x0F_0000 plus (0x1_0000 minus XGRAMSIZE)1
1 XGRAMSIZE is the hexadecimal value of XGATE RAM SIZE in bytes.
XGATE FLASH
XGFLASH_HIGH = 0x78_0000 plus (0xFFFF minus XGRAMSIZE)