
Central Processing Unit (CPU)
Technical Data
MC68HC908GR8 — Rev 4.0
154
Central Processing Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
10.9 Opcode Map
See
Table 10-2
.
TST
opr
TSTA
TSTX
TST
opr
,X
TST ,X
TST
opr
,SP
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0 – –
–
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
TSX
Transfer SP to H:X
H:X
←
(SP) + 1
– – – – – – INH
95
2
TXA
Transfer X to A
A
←
(X)
– – – – – – INH
9F
1
TXS
Transfer H:X to SP
(SP)
←
(H:X) – 1
– – – – – – INH
94
2
A Accumulator
n
CCarry/borrow bit
opr
CCRCondition code registerPC
ddDirect address of operandPCH
dd rrDirect address of operand and relative offset of branch instructionPCL
DDDirect to direct addressing modeREL
DIRDirect addressing mode
rel
DIX+Direct to indexed with post increment addressing moderr
ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1
EXTExtended addressing modeSP2
ff Offset byte in indexed, 8-bit offset addressingSP
HHalf-carry bitU
HIndex register high byteV
hh llHigh and low bytes of operand address in extended addressingX
I Interrupt maskZ
ii Immediate operand byte&
IMDImmediate source to direct destination addressing mode|
IMMImmediate addressing mode
⊕
INHInherent addressing mode( )
IXIndexed, no offset addressing mode–( )
IX+Indexed, no offset, post increment addressing mode#
IX+DIndexed with post increment to direct addressing mode
IX1Indexed, 8-bit offset addressing mode
←
IX1+Indexed, 8-bit offset, post increment addressing mode
IX2Indexed, 16-bit offset addressing mode:
MMemory location
NNegative bit—
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
Table 10-1. Instruction Set Summary (Continued)
Source
Form
Operation
Description
Effect on
CCR
A
M
O
O
C
V H I N Z C
F
Freescale Semiconductor, Inc.
n
.