
Central Processor Unit (CPU)
MC68HC908AP A-Family Data Sheet, Rev. 3
60
Freescale Semiconductor
4.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by:
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU
to normal operation if the break interrupt has been deasserted.
4.7 Instruction Set Summary
Table 4-1 provides a summary of the M68HC08 instruction set.
4.8 Opcode Map
Table 4-1. Instruction Set Summary
Source
Form
Operation
Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VH I N Z C
ADC #opr
ADC opr
ADC opr,X
ADC ,X
ADC opr,SP
Add with Carry
A
← (A) + (M) + (C)
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A9
B9
C9
D9
E9
F9
9EE9
9ED9
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
ADD #opr
ADD opr
ADD opr,X
ADD ,X
ADD opr,SP
Add without Carry
A
← (A) + (M)
–
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AB
BB
CB
DB
EB
FB
9EEB
9EDB
ii
dd
hh ll
ee ff
ff
ee ff
2
3
4
3
2
4
5
AIS #opr
Add Immediate Value (Signed) to SP
SP
← (SP) + (16 M)
– – – – – – IMM
A7
ii
2
AIX #opr
Add Immediate Value (Signed) to H:X
H:X
← (H:X) + (16 M)
– – – – – – IMM
AF
ii
2