參數(shù)資料
型號： MC88915TFN55
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 時鐘及定時
英文描述： 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28
封裝： PLASTIC, LCC-28
文件頁數(shù)： 18/18頁
文件大?。?/td> 401K
代理商： MC88915TFN55
MC88915T
34
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
MC88915TFN133 (Continued)
Table 16. AC Characteristics (TA = –40°C to +85°C, VCC = 5.0 V ± 5%, Load = 50 Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
Condition
tRISE/FALL
Outputs
Rise/Fall Time, All Outputs
(Between 0.2 VCC and 0.8 VCC)
1.0
2.5
ns
Into a 50
Load
Terminated to VCC/2
tRISE/FALL1
2X_Q Output
1. These specifications are not tested. They are guaranteed by statistical characterization. See AC specification Note 1.
Rise/Fall Time into a 20 pF Load, with Termination
Specified in Note2
2. tCYCLE in this spec is 1/Frequency at which the particular output is running.
0.5
1.6
ns
tRISE: 0.8 V – 2.0 V
tFALL: 2.0 V – 0.8 V
tPULSEWIDTH1
(Q0–Q4, Q5, Q/2)
Output Pulse Width: Q0, Q1, Q2, Q4, Q4,
Q5, Q/2 @ VCC/2
0.5 tCYCLE – 0.52 0.5 tCYCLE + 0.52
ns
Into a 50
Load
Terminated to VCC/2
tPULSEWIDTH1
(2X_Q Output)
Output Pulse Width:
66 – 133 MHz
2X_Q @ 1.5 V
40 – 65 MHz
0.5 tCYCLE – 0.52
0.5 tCYCLE – 0.9
0.5 tCYCLE + 0.52
0.5 tCYCLE + 0.9
ns
Must Use Termination
Specified in Note2
tPULSEWIDTH1
(2X_Q Output)
Output Pulse Width:
66 – 133 MHz
2X_Q @ VCC/2
40 – 65 MHz
0.5 tCYCLE – 0.52
0.5 tCYCLE – 0.9
0.5 tCYCLE + 0.52
0.5 tCYCLE + 0.9
ns
Into a 50
Load
Terminated to VCC/2
tPD1,3
SYNC Feedback
3. The tPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1
and FEEDBACK Input Pins)
(With 1 M
from RC1 to An VCC)
ns
See Note4 and Figure 4 for
Detailed Explanation
4. Under equally loaded conditions and at a fixed temperature and voltage.
–1.05
–0.25
(With 1 M
from RC1 to An GND)
+1.25
+3.25
tSKEWr1,4
(Rising)5
5. With VCC fully powered on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 F, tLOCK minimum is with
C1 = 0.01
F.
Output-to-Output Skew Between Outputs Q0–Q4,
Q/2 (Rising Edges Only)
—
500
ps
All Outputs into a Matched
50
Load Terminated to
VCC/2
tSKEWf1,4
(Falling)
Output-to-Output Skew Between Outputs Q0–Q4
(Falling Edges Only)
—
500
ps
All Outputs into a Matched
50
Load Terminated to
VCC/2
tSKEWall1,4
Output-to-Output Skew 2X_Q, Q/2, Q0–Q4 Rising,
Q5 Falling
—
750
ps
All Outputs into a Matched
50
Load Terminated to
VCC/2
tLOCK5
Time Required to Acquire Phase-Lock from Time
SYNC Input Signal is Received
1.0
10
ms
Also Time to LOCK
Indicator High
tPZL6
6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates. The final guaranteed values will be available when “MC” status is
reached.
Output Enable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
3.0
14
ns
Measured with the PLL_EN
Pin Low
tPHZ, tPLZ6
Output Disable Time OE/RST to 2X_Q, Q0–Q4,
Q5, and Q/2
3.0
14
ns
Measured with the PLL_EN
Pin Low
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