參數資料
型號: MC8641VU1250NC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, CBGA1023
封裝: 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
文件頁數: 51/140頁
文件大?。?/td> 1484K
代理商: MC8641VU1250NC
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
18
Freescale Semiconductor
RESET Initialization
NOTE
The phase between the output clocks TSEC1_GTX_CLK and
TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase
between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK
(ports 3 and 4) is no more than 100 ps.
4.4
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC,
see the specific section of this document.
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8641. Table 11 provides the RESET initialization AC timing specifications.
EC
n_GTX_CLK125 duty cycle
GMII, TBI
1000Base-T for RGMII, RTBI
tG125H/tG125
45
47
55
53
%1, 2
Notes:
1. Timing is guaranteed by design and characterization.
2. EC
n_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation.
EC
n_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle
generated by the eTSEC GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications” for duty cycle
for 10Base-T and 100Base-T reference clock.
3. ±100 ppm tolerance on EC
n_GTX_CLK125 frequency
Table 11. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
100
μs
Minimum assertion time for SRESET_0 & SRESET_1
3
SYSCLKs
1
Platform PLL input setup time with stable SYSCLK
before HRESET negation
100
μs2
Input setup time for POR configs (other than PLL
config) with respect to negation of HRESET
4
SYSCLKs
1
Input hold time for all POR configs (including PLL
config) with respect to negation of HRESET
2
SYSCLKs
1
Table 10. EC
n_GTX_CLK125 AC Timing Specifications (continued)
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