參數(shù)資料
型號(hào)： MC8641HX1500KB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 166.66 MHz, MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, CERAMIC, BGA-1023
文件頁數(shù)： 56/130頁
文件大小： 1493K
代理商： MC8641HX1500KB
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
31
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source-synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is
relationship between the maximum FIFO speed and the platform speed. For more information see
NOTE
The phase between the output clocks TSEC1_GTX_CLK and
TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase
between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK
(ports 3 and 4) is no more than 100 ps.
A summary of the FIFO AC specifications appears in Table 26 and Table 27.
Table 26. FIFO Mode Transmit AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TX_CLK, GTX_CLK clock period (GMII mode)
tFIT
7.0
8.0
100
ns
TX_CLK, GTX_CLK clock period (Encoded mode)
tFIT
5.3
8.0
100
ns
TX_CLK, GTX_CLK duty cycle
tFITH/tFIT
45
50
55
%
TX_CLK, GTX_CLK peak-to-peak jitter
tFITJ
——
250
ps
Rise time TX_CLK (20%–80%)
tFITR
—
0.75
ns
Fall time TX_CLK (80%–20%)
tFITF
—
0.75
ns
FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK
tFITDV
2.0
—
ns
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
tFITDX
0.5
—
3.0
ns
Table 27. FIFO Mode Receive AC Timing Specification
At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period (GMII mode)
tFIR
1
1 ±100 ppm tolerance on RX_CLK frequency
7.0
8.0
100
ns
RX_CLK clock period (Encoded mode)
tFIR
5.3
8.0
100
ns
RX_CLK duty cycle
tFIRH/tFIR
45
50
55
%
RX_CLK peak-to-peak jitter
tFIRJ
—
250
ps
Rise time RX_CLK (20%–80%)
tFIRR
—
0.75
ns
Fall time RX_CLK (80%–20%)
tFIRF
—
0.75
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tFIRDV
1.5
—
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tFIRDX
0.5
—
ns
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MC8641DHX1250HB 32-BIT, 166.66 MHz, MICROPROCESSOR, CBGA1023
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