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參數(shù)資料
| 型號： | MC8641DVU1250HC |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 166.66 MHz, MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023 |
| 文件頁數(shù)： | 9/130頁 |
| 文件大?。?/td> | 1493K |
| 代理商： | MC8641DVU1250HC |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
106
Freescale Semiconductor
Clocking
18.2
MPX to SYSCLK PLL Ratio
The MPX clock is the clock that drives the MPX bus, and is also called the platform clock. The frequency
of the MPX is set using the following reset signals, as shown in Table 68:
SYSCLK input signal
Table 65. Memory Bus Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
Unit
Notes
1000, 1250, 1333, 1500MHz
Min
Max
Memory bus clock frequency
200
300
MHz
1, 2
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,”
for ratio settings.
2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock frequency.
Table 66. Platform/MPX bus Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
Unit
Notes
1000, 1250, 1333, 1500MHz
Min
Max
Platform/MPX bus clock frequency
400
500-600
MHz
1, 2
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 18.2, “MPX to SYSCLK PLL Ratio,” and Section 18.3, “e600 to MPX clock PLL Ratio,”
for ratio settings.
2. Platform/MPX frequencies between 400 and 500 MHz are not supported.
Table 67. Local Bus Clocking Specifications
Characteristic
Maximum Processor Core
Frequency
Unit
Notes
1000, 1250, 1333, 1500MHz
Min
Max
Local bus clock speed (for Local Bus Controller)
25
133
MHz
1
Notes:
1. The Local bus clock speed on LCLK[0:2] is determined by MPX clock divided by the Local Bus PLL ratio programmed in
LCRR[CLKDIV]. See the reference manual for the MPC8641D for more information on this.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8641DVU1250J | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641DVU1250K | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641DVU1250N | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8641DVU1333CJE | 制造商:Freescale Semiconductor 功能描述:G8,REV3,0.95V,105C - Trays |
| MC8641DVU1333G | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
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