參數(shù)資料
型號： MC8641DVU1250GC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
文件頁數(shù)： 82/140頁
文件大?。?/td> 1484K
代理商： MC8641DVU1250GC
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
46
Freescale Semiconductor
Local Bus
Figure 25 provides the AC test load for the local bus.
Local bus clock to output valid (except
LAD/LDP and LALE)
tLBKHOV1
—2.0
ns
Local bus clock to data valid for
LAD/LDP
tLBKHOV2
—2.2
ns
Local bus clock to address valid for
LAD
tLBKHOV3
—2.3
ns
Local bus clock to LALE assertion
tLBKHOV4
—2.3
ns
3
Output hold from local bus clock
(except LAD/LDP and LALE)
tLBKHOX1
0.7
—
ns
Output hold from local bus clock for
LAD/LDP
tLBKHOX2
0.7
—
ns
3
Local bus clock to output high
Impedance (except LAD/LDP and
LALE)
tLBKHOZ1
—2.5
ns
5
Local bus clock to output high
impedance for LAD/LDP
tLBKHOZ2
—2.5
ns
5
Note:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional
block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional
block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing
(LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the
tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output
hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL
bypass mode.
3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN for PLL enabled or
internal local bus clock for PLL bypass mode to 0.4
× OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when
the total current delivered through the component pin is less than or equal to the leakage
current specification.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any
change in LAD. tLBOTOT is programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew
measured between complementary signals at BVDD/2.
8. Guaranteed by design.
Table 41. Local Bus Timing Parameters (OVDD = 3.3 V)m - PLL Enabled (continued)
Parameter
Symbol 1
Min
Max
Unit
Notes
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