參數(shù)資料
型號(hào)： MC8641DHX1500NB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
文件頁數(shù)： 107/140頁
文件大?。?/td> 1484K
代理商： MC8641DHX1500NB
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
69
High-Speed Serial Interfaces (HSSI)
Figure 47. Differential Measurement Points for Rise and Fall Time
Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes Reference Clocks is defined by each interface protocol
based on application usage. Refer to the following sections for detailed information:
Rising edge rate (SD
n_REF_CLK) to falling edge rate
(SD
n_REF_CLK) matching
Rise-Fall
Matching
—20
%
1, 4
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from -200 mV to +200 mV on the differential waveform (derived from SD
n_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered
on the differential zero crossing. See Figure 47.
4. Matching applies to rising edge rate for SD
n_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200
mV window centered on the median cross point where SDn_REF_CLK rising meets SD
n_REF_CLK falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate
of SD
n_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 48.
Table 47. SerDes Reference Clock Common AC Parameters (continued)
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5% and 1.05V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
VIH = +200 mV
VIL = -200 mV
0.0 V
SD
n_REF_CLK
minus
SD
n_REF_CLK
SD
n_REF_CLK
SD
n_REF_CLK
SD
n_REF_CLK
SD
n_REF_CLK
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