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| 型號： | MC8640TVU1250HC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 6/130頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU DUAL E600 994-FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.25GHz |
| 電壓： | 1.05V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 994-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 994-FCCBGA（33x33） |
| 包裝： | 托盤 |
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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
103
Signal Listings
Note:
1. Multi-pin signals such as D1_MDQ[0:63] and D2_MDQ[0:63] have their physical package pin numbers listed in order
corresponding to the signal names.
2. Stub Series Terminated Logic (SSTL-18 and SSTL-25) type pins.
3. If a DDR port is not used, it is possible to leave the related power supply (Dn_GVDD, Dn_MVREF) turned off at reset. Note
that these power supplies can only be powered up again at reset for functionality to occur on the DDR port.
4. Low Voltage Differential Signaling (LVDS) type pins.
5. Low Voltage Transistor-Transistor Logic (LVTTL) type pins.
6. This pin is a reset configuration pin and appears again in the Reset Configuration Signals section of this table. See the Reset
Configuration Signals section of this table for config name and connection details.
7. Recommend a weak pull-up resistor (1–10 k
Ω) be placed from this pin to its power supply.
8. Recommend a weak pull-down resistor (2–10 k
Ω) be placed from this pin to ground.
9. This multiplexed pin has input status in one mode and output in another
10. This pin is a multiplexed signal for different functional blocks and appears more than once in this table.
11. This pin is open drain signal.
12. Functional only on the MPC8640D.
13. These pins should be left floating.
14. These pins should be connected to SVDD.
15. These pins should be pulled to ground with a strong resistor (270-
Ω to 330-Ω).
16. These pins should be connected to OVDD.
17.This is a SerDes PLL/DLL digital test signal and is only for factory use.
18. This is a SerDes PLL/DLL analog test signal and is only for factory use.
19. This pin should be pulled to ground with a 100-
Ω resistor.
20. The pins in this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when
the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k
Ω pull-down
resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down
the value of the net at reset, then a pullup or active driver is needed.
21. Should be pulled down at reset if platform frequency is at 400 MHz.
22. These pins require 4.7-k
Ω pull-up or pull-down resistors and must be driven as they are used to determine PLL configuration
ratios at reset.
23. This output is actively driven during reset rather than being released to high impedance during reset.
24 These JTAG pins have weak internal pull-up P-FETs that are always enabled.
25. This pin should NOT be pulled down (or driven low) during reset.
26.These are test signals for factory use only and must be pulled up (100-
Ω to 1- kΩ.) to OVDD for normal machine operation.
27. Dn_MDIC[0] should be connected to ground with an 18-
Ω resistor ± 1-Ω and Dn_MDIC[1] should be cLonnected Dn_GVDD
with an 18-
Ω resistor ± 1-Ω. These pins are used for automatic calibration of the DDR IOs.
28. Pin N18 is recommended as a reference point for determining the voltage of VDD_PLAT and is hence considered as the
VDD_PLAT sensing voltage and is called SENSEVDD_PLAT.
29. Pin P18 is recommended as the ground reference point for SENSEVDD_PLAT and is called SENSEVSS_PLAT.
30.This pin should be pulled to ground with a 200-
Ω resistor.
31.These pins are connected to the power/ground planes internally and may be used by the core power supply to improve
tracking and regulation.
32. Must be tied low if unused
33. These pins may be used as defined functional reset configuration pins in the future. Please include a resistor pull-up/down
option to allow flexibility of future designs.
34. Used as serial data output for serial RapidIO 1
×/4× link.
35. Used as serial data input for serial RapidIO 1
×/4× link.
36.This pin requires an external 4.7-k
Ω pull-down resistor to prevent PHY from seeing a valid transmit enable before it is actively
driven.
Table 63. MPC8640 Signal Reference by Functional Block (continued)
Name1
Package Pin Number
Pin Type
Power Supply
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 345-012-542-204 | CARDEDGE 12POS DUAL .100 GREEN |
| MC8640TVU1067NC | MPU DUAL E600 994-FCCBGA |
| 345-012-542-202 | CARDEDGE 12POS DUAL .100 GREEN |
| 345-012-542-201 | CARDEDGE 12POS DUAL .100 GREEN |
| MPC8533EVTANG | MPU POWERQUICC 783-PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8640TVU1250HE | 功能描述:微處理器 - MPU G8 REV3.0 0.95V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC8640TVU1250N | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC Series |
| MC8640VU1000H | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8640VU1000HC | 功能描述:微處理器 - MPU G8 REV2.1 1.05V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC8640VU1000HE | 功能描述:微處理器 - MPU G8 REV 3.0 1.05V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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