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參數(shù)資料
| 型號： | MC80F0224K |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 98/128頁 |
| 文件大?。?/td> | 1408K |
| 代理商： | MC80F0224K |
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MC80F0208/16/24
Preliminary
94
MAR. 2005 Ver 0.2
20. OPERATION MODE
The system clock controller starts or stops the main-frequency
clock oscillator. The operating mode is generally divided into the
main active mode. Figure 20-1 shows the operating mode transi-
tion diagram.
System clock control is performed by the system clock mode reg-
ister, SCMR. During reset, this register is initialized to “0” so that
the main-clock operating mode is selected.
Main Active Mode
This mode is fast-frequency operating mode. The CPU and the
peripheral hardware are operated on the high-frequency clock. At
reset release, this mode is invoked.
SLEEP Mode
In this mode, the CPU clock stops while peripherals and the os-
cillation source continues to operate normally.
STOP Mode
In this mode, the system operations are all stopped, holding the
internal states valid immediately before the stop at the low power
consumption level. The main oscillation source stops, but the sub
clock oscillation and watch timer by sub clock and RC-oscillated
watchdog timer don’t stop.
Figure 20-1 Operating Mode
20.1 Operation Mode Switching
In the Main active mode, only the high-frequency clock oscillator
is used. In the Sub active mode, the low-frequency clock oscilla-
tion is used, so the low power voltage operation or the low power
consumption operation can be enabled. Instruction execution
does not stop during the change of operation mode. In this case,
some peripheral hardware capabilities may be affected. For de-
tails, refer to the description of the relevant operation.
The following describes the switching between the Main active
mode and the Sub active mode. During reset, the system clock
mode register is initialized at the Main active mode. It must be set
to the Sub active mode for reducing the power consumption.
Shifting from the Normal operation to the SLEEP mode
If the CPU clock stops and the SLEEP mode is invoked, the CPU
stops while other peripherals are operate normally.
The ways of release from this mode are by setting the RESET pin
to low and all available interrupts. For more detail, See "21.
POWER SAVING OPERATION" on page 95.
Shifting from the Normal operation to the STOP mode
If the main-frequency clock oscillation stops and the STOP mode
is invoked, the CPU stops and other peripherals are stop too. But
sub-frequency clock oscillation operate continuously if enabled
previously. After the STOP operation is released by reset, the op-
eration mode is changed to Main active mode.
The methods of release from this mode are Reset, Watch Timer,
Timer/Event counter, SIO(External clock), UART, and External
Interrupt.
For more details, see "21. POWER SAVING OPERATION" on
page 95.
Note:
In the STOP and SLEEP operating modes, the pow-
er consumption by the oscillator and the internal hardware
is reduced. However, the power for the pin interface (de-
pending on external circuitry and program) is not directly
associated with the low-power consumption operation. This
must be considered in system design as well as interface
circuit design.
Main Active
Mode
Main : Oscillation or Stop
Sub : Oscillation
System Clock : Stop
Main : Oscillation
Sub : Oscillation or stop
System Clock : Main
Stop / Sleep
Mode
* Note1 / * Note2
* Note1 : Stop released by Reset,
Watch Timer, Watchdog Timer
Timer(event counter), External interrupt,
SIO (External clock), UART0, UART1
* Note2 : Sleep released by
Reset, or All interrupts
* Note3
* Note3 :
1) Stop mode Admission
LDM SSCR, #5AH
STOP
NOP
NOP
2) Sleep mode Admission
LDM SSCR, #0FH
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