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參數(shù)資料
| 型號： | MC80F0224K |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 63/128頁 |
| 文件大小： | 1408K |
| 代理商： | MC80F0224K |
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Preliminary
MC80F0208/16/24
MAR. 2005 Ver 0.2
59
Figure 14-12 Timer 4 for only 16 bit mode
14.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer mode reg-
ister TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as
shown in Figure 14-13. Likewise, the Timer 2 capture mode is set
by bit CAP2 of timer mode register TM2 (bit CAP3 of timer
mode register TM3 for Timer 3) as shown in Figure 14-14.
The Timer/Counter register is increased in response internal or
external input. This counting function is same with normal timer
mode, and Timer interrupt is generated when timer register T0
(T1, T2, T3) increases and matches TDR0 (TDR1, TDR2,
TDR3).
This timer interrupt in capture mode is very useful when the pulse
width of captured signal is more wider than the maximum period
of Timer.
For example, in Figure 14-16, the pulse width of captured signal
is wider than the timer data value (FF
H
) over 2 times. When ex-
ternal interrupt is occurred, the captured value (13
H
) is more little
than wanted value. It can be obtained correct value by counting
the number of timer overflow occurrence.
Timer/Counter still does the above, but with the added feature
that a edge transition at external input INTx pin causes the current
value in the Timer x register (T0,T1,T2,T3), to be captured into
registers CDRx (CDR0, CDR1, CDR2, CDR3), respectively. Af-
ter captured, Timer x register is cleared and restarts by hardware.
It has three transition modes: "falling edge", "rising edge", "both
edge" which are selected by interrupt edge selection register
IEDS. Refer to “19.5 External Interrupt” on page 92. In addition,
the transition at INT
n
pin generate an interrupt.
Note:
The CDRn and TDRn are in same address.In the
capture mode, reading operation is read the CDRn, not
TDRn because path is opened to the CDRn.
clear
0: Stop
1: Clear and start
T4ST
T4CN
TDR4H + TDR4L
(16-bit)
Comparator
Higher byte Lower byte
COMPARE DATA
T4H + T4L
(16-bit)
INITIAL VALUE: 00
H
ADDRESS: 0DC
H
TM4
X means don’t care
BTCL
T4CK1
7
-
6
-
5
4
3
2
1
0
T4CN T4ST
T4CK0
CAP4 T4CK2
X
X
X
X
X
X
0
X
÷
2
÷
4
÷
8
X
IN
PIN
MUX
P
T4CK[2:0]
111
000
001
010
011
÷
256
÷
1024
100
101
110
T4IF
TIMER 4
INTERRUPT
÷
2048
÷
64
÷
16
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