MC80F0208/16/24
Preliminary
54
MAR. 2005 Ver 0.2
Example 1:
Timer0 = 2ms 8-bit timer mode at 4MHz
Timer1 = 0.5ms 8-bit timer mode at 4MHz
Timer2 = 1ms 8-bit timer mode at 4MHz
Timer3 = 1ms 8-bit timer mode at 4MHz
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
SET1
SET1
SET1
SET1
EI
TDR0,#249
TDR1,#249
TDR2,#249
TDR3,#249
TM0,#0000_1111B
TM1,#0000_1011B
TM2,#0000_1111B
TM3,#0000_1011B
T0E
T1E
T2E
T3E
Example 2:
Timer0 = 8-bit event counter mode
Timer1 = 0.5ms 8-bit timer mode at 4MHz
Timer2 = 8-bit event counter mode
Timer3 = 1ms 8-bit timer mode at 4MHz
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
SET1
SET1
SET1
SET1
EI
TDR0,#249
TDR1,#249
TDR2,#249
TDR3,#249
TM0,#0001_1111B
TM1,#0000_1011B
TM2,#0001_1111B
TM3,#0000_1011B
T0E
T1E
T2E
T3E
These timers have each 8-bit count register and data register. The
count register is increased by every internal or external clock in-
put. The internal clock has a prescaler divide ratio option of 2, 4,
8, 32, 128, 512, 2048 selected by control bits T0CK[2:0] of reg-
ister TM0 or 1, 2, 8 selected by control bits T1CK[1:0] of register
TM1, or 2, 4, 8, 16, 64, 256, 1024 selected by control bits
T2CK[2:0] of register TM2, or 1, 4, 16 selected by control bits
T3CK[1:0] of register TM3. In the Timer 0, timer register T0 in-
creases from 00
H
until it matches TDR0 and then reset to 00
H
.
The match output of Timer 0 generates Timer 0 interrupt (latched
in T0IF bit).
In counter function, the counter is increased every 0-to-1(1-to-0)
(rising & falling edge) transition of EC0 pin. In order to use
counter function, the bit EC0 of the Port Selection Regis-
ter(PSR0.4) is set to "1". The Timer 0 can be used as a counter by
pin EC0 input, but Timer 1 can not. Likewise, In order to use
Timer2 as counter function, the bit EC1 of the Port Selection
Register(PSR0.5) is set to "1". The Timer 2 can be used as a
counter by pin EC1 input, but Timer 3 can not.
14.1.1 8-bit Timer Mode
In the timer mode, the internal clock is used for counting up.
Thus, you can think of it as counting internal clock input. The
contents of TDR
n
are compared with the contents of up-counter,
T
n
. If match is found, a timer
n
interrupt (T
n
IF) is generated and
the up-counter is cleared to 0. Counting up is resumed after the
up-counter is cleared.
As the value of TDR
n
is changeable by software, time interval is
set as you want
Figure 14-6 Timer Mode Timing Chart
0
n-2
2
0
n
3
n-1
n
Source clock
Up-counter
TDR1
T1IF interrupt
Start count
1
2
3
1
4
Match
Detect
Counter
Clear
~
~
~
~
~