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參數(shù)資料
| 型號： | MC80F0208Q |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 49/128頁 |
| 文件大?。?/td> | 1408K |
| 代理商： | MC80F0208Q |
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Preliminary
MC80F0208/16/24
MAR. 2005 Ver 0.2
45
Figure 12-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is generated,
which drives the RESET pin low to reset the internal hardware.
The main clock oscillator also turns on when a watchdog timer
reset is generated in sub clock mode.
The WDTIF bit of IFR register is set when watchdog timer inter-
rupt is generated. (Refer to Figure 12-4)
Figure 12-4 IFR(Interrupt Flag Register)
2
3
n
Source clock
BIT overflow
Binary-counter
WDTR
WDTIF interrupt
WDTR
←
“1000_0011
B
”
1
0
Match
Detect
Counter
Clear
1
2
3
0
3
WDT reset
reset
Counter
Clear
NOTE1 : In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR
in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and
Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after
reading this register.
R/W
-
INITIAL VALUE: --00 0000
B
ADDRESS: 0DF
H
IFR
-
MSB
R/W
UART0 Tx interrupt occurred flag
NOTE3
UART0 Rx interrupt occurred flag
NOTE3
LSB
R/W
R/W
R/W
R/W
RX0IOF
TX0IOF
WTIOF
WDT interrupt occurred flag
NOTE1
WT interrupt occurred flag
NOTE1
UART1 Tx interrupt occurred flag
NOTE2
UART1 Rx interrupt occurred flag
NOTE2
RX1IOF TX1IOF
WDTIOF
NOTE2 : In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt
service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared
with interrupt vector address. These flag bits must be cleared by software after reading this register.
NOTE3 : In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt
service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared
with interrupt vector address. These flag bits must be cleared by software after reading this register.
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