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2513L–AVR–03/2013
ATmega162/V
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SPMEN bits in SPMCR. When an LPM instruction is executed within three cycles after the
BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse Low byte (FLB) will be
description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR,
the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction
is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the
value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
Preventing Flash
Corruption
During periods of low V
CC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1.
If there is no need for a Boot Loader update in the system, program the Boot Loader
Lock bits to prevent any Boot Loader software updates.
2.
Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating volt-
age matches the detection level. If not, an external low V
CC Reset Protection circuit can
be used. If a Reset occurs while a write operation is in progress, the write operation will
be completed provided that the power supply voltage is sufficient.
3.
Keep the AVR core in Power-down sleep mode during periods of low V
CC. This will pre-
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCR Register and thus the Flash from unintentional writes.
Bit
7
65
4
3
210
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Bit
7
65
4
3
210
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Bit
7
65
4
3
210
Rd
–
EFB4
EFB3
EFB2
EFB1
–