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參數(shù)資料
| 型號： | MC80C52EXXX-12SB |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, SIDE BRAZED, DIP-40 |
| 文件頁數(shù)： | 86/109頁 |
| 文件大小： | 10824K |
| 代理商： | MC80C52EXXX-12SB |
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63
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Be aware that the COM0x[1:0] bits are not double buffered together with the compare value. Changing the COM0x[1:0]
bits will take effect immediately.
11.6
Compare Match Output Unit
The Compare Output mode (COM0x[1:0]) bits have two functions. The Waveform Generator uses the COM0x[1:0] bits
for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x[1:0] bits control the OC0x
pin output source. Figure 11-4 on page 63 shows a simplified schematic of the logic affected by the COM0x[1:0] bit
setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port
Control Registers (DDR and PORT) that are affected by the COM0x[1:0] bits are shown. When referring to the OC0x
state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x Register is
reset to “0”.
Figure 11-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the
COM0x[1:0] bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction
Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output
before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that
some COM0x[1:0] bit settings are reserved for certain modes of operation, see “Register Description” on page 69
11.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0x[1:0] bits differently in Normal, CTC, and PWM modes. For all modes, setting
the COM0x[1:0] = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next
Compare Match. For compare output actions in the non-PWM modes refer to Table 11-2 on page 70. For fast PWM
mode, refer to Table 11-3 on page 70, and for phase correct PWM refer to Table 11-4 on page 70.
PORT
DDR
DQ
OCn
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
D
ATA
B
U
S
FOCn
clk
I/O
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