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參數(shù)資料
| 型號(hào)： | MC80C52EXXX-12SB |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | 0.600 INCH, SIDE BRAZED, DIP-40 |
| 文件頁(yè)數(shù)： | 100/109頁(yè) |
| 文件大?。?/td> | 10824K |
| 代理商： | MC80C52EXXX-12SB |
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76
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
12.
16-bit Timer/Counter1
12.1
Features
True 16-bit Design (i.e., Allows 16-bit PWM)
Two independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
12.2
Overview
The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and
signal timing measurement.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 12-1 on page 76. For actual placement of I/O
pins, refer to “SOIC/TSSOP” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold.
The device-specific I/O Register and bit locations are listed in section “Register Description” on page 96.
Figure 12-1. 16-bit Timer/Counter Block Diagram
Clock Select
Timer/Counter
D
ATA
B
U
S
OCRnA
OCRnB
ICRn
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP
BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA
TCCRnB
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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