參數(shù)資料
型號(hào)： MC80C52CXXX-12SB
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
文件頁(yè)數(shù)： 3/80頁(yè)
文件大?。?/td> 5152K
代理商： MC80C52CXXX-12SB
195
2466T–AVR–07/10
ATmega16(L)
Figure 91. Formats and States in the Slave Receiver Mode
Slave Transmitter
Mode
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver
(see Figure 92). All the status codes mentioned in this section assume that the prescaler bits are
zero or are masked to zero.
Figure 92. Data Transfer in Slave Transmitter Mode
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
S
SLA
W
A
DATA
A
$60
$80
$88
A
$68
Reception of the own
slave address and one or
more data bytes. All are
acknowledged
Last data byte received
is not acknowledged
Arbitration lost as master
and addressed as slave
Reception of the general call
address and one or more data
bytes
Last data byte received is
not acknowledged
n
From master to slave
From slave to master
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-wire Serial Bus. The
prescaler bits are zero or masked to zero
P or S
DATA
A
$80
$A0
P or S
A
DATA
A
$70
$90
$98
A
$78
P or S
DATA
A
$90
$A0
P or S
A
General Call
Arbitration lost as master and
addressed as slave by general call
DATA
A
TWAR
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
Value
Device’s Own Slave Address
Device 3
Device n
SDA
SCL
........
R1
R2
V
CC
Device 2
MASTER
RECEIVER
Device 1
SLAVE
TRANSMITTER
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