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參數(shù)資料
| 型號： | MC80C32E-12/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 12 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁數(shù)： | 43/46頁 |
| 文件大小： | 7004K |
| 代理商： | MC80C32E-12/883D |
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671
32117D–AVR-01/12
AT32UC3C
26.8.1
Control Register
Name:
CR
Access Type:
Write-only
Offset:
0x00
Reset Value:
0x00000000
LASTXFER: Last Transfer
1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this
allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD
transfer has completed.
0: Writing a zero to this bit has no effect.
FLUSHFIFO: Flush Fifo Command
1: If The FIFO Mode is enabled (MR.FIFOEN written to one) and if an overrun error has been detected, this command allows to
empty the FIFO.
0: Writing a zero to this bit has no effect.
SWRST: SPI Software Reset
1: Writing a one to this bit will reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in
slave mode after software reset. Peripheral DMA Controller channels are not affected by software reset.
0: Writing a zero to this bit has no effect.
SPIDIS: SPI Disable
1: Writing a one to this bit will disable the SPI. As soon as SPIDIS is written to one, the SPI finishes its transfer, all pins are set
in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is
disabled. If both SPIEN and SPIDIS are equal to one when the CR register is written, the SPI is disabled.
0: Writing a zero to this bit has no effect.
SPIEN: SPI Enable
1: Writing a one to this bit will enable the SPI to transfer and receive data.
0: Writing a zero to this bit has no effect.
31
30
29
28
27
26
25
24
-
---
--
-
LASTXFER
23
22
21
20
19
18
17
16
-
---
--
15
14
13
12
11
10
9
8
-
---
--
-
FLUSHFIFO
76
543
21
0
SWRST
-
SPIDIS
SPIEN
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